FPGA implementation of Singular Value Decomposition
نویسندگان
چکیده
Singular value decomposition has been used in signal processing, image processing, principal component analysis, robotics and my other real time applications. These applications demand fast processing of large datasets. SVD needs large amount of computation. In this paper, we present the parallel implementation of Singular Value Decomposition in FGPA. SVD is implemented using two sided Jacobi algorithm to attain parallel systolic array architecture. The diagonal processing elements compute the rotation parameter and propagate to other off-diagonal processing elements in row and column for row and column operations respectively. The CORDIC algorithm is used in each processing element and optimized to have one bit rotation parameter which reduces the hardware requirement and routing overhead. The design has been tested and verified in Xilinx Spartan-6 LX45 FPGA for 4x4 asymmetric matrix. Keywords—SVD; Jacobi algorithm; FPGA; CORDIC
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